An All-digital, Cyclic and Synthesizable TDC in the ADPLL-based Clocking Digital Systems for Multidomain Power Management

被引：0

作者：

Chen, Shao-Hua ^{[1
]}

Lin, Ming-Bo ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, Dept Elect Engn, Taipei, Taiwan

来源：

Advance Materials Development and Applied Mechanics | 2014年 / 597卷

关键词：

all-digital phase-locked loop (ADPLL); dynamic voltage and frequency scaling (DVFS); system-on-chip (SoC) and time-to-digital converter (TDC);

D O I：

10.4028/www.scientific.net/AMM.597.515

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

In this paper, we propose an all-digital, cyclic and synthesizable TDC architecture, which may be used as a core block in ADPLLs to replace the analog block as a phase/frequency detector and a charge pump. Traditional designs of the DVFS scheme for multidomain power management are based on a conventional analog PLL to generate the dynamic voltage and frequency in which the use of a digital TDC eliminates the need for current sources in conventional analog PLLs.

引用

页码：515 / 518

页数：4

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