Analysis of Digital Bang-Bang Clock and Data Recovery for Multi-Gigabit/s Serial Transceivers

被引：0

作者：

Sun, Yehui ^{[1
]}

Wang, Hui ^{[1
]}

机构：

[1] Integrated Device Technol, Shanghai 200233, Peoples R China

来源：

PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A Harmonic Balance method for analyzing digital bang-bang clock and data recovery (CDR) is proposed in this paper. The jitter tolerance performance of the CDR is predicted by a function with variables that can be easily correlated to design parameters. A 6.25Gb/s serial transceiver was fabricated in 90nm CMOS technology. Measurements show that the jitter tolerance performance can be accurately predicted by the proposed method.

引用

页码：343 / 346

页数：4

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