Modeling of jitter in bang-bang clock and data recovery circuits

被引：15

作者：

Lee, J ^{[1
]}

Kundert, KS ^{[1
]}

Razavi, B ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249492

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an approach to analyzing bang-bang CDR loops, predicting performance aspects such as jitter Din transfer, jitter tolerance, jitter generation, and the bit error rate. A 1-Gb/s CDR circuit realized in 0.35-mum CMOS technology validates the theoretical results.

引用

页码：711 / 714

页数：4

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