Performance evaluation of deep sub-micron, fully-depleted silicon-on-insulator (FD-SOI) transistors at low temperatures

被引:0
|
作者
Yuan, J [1 ]
Patel, JU [1 ]
Vandooren, A [1 ]
机构
[1] CALTECH, Jet Prop Lab, Pasadena, CA 91109 USA
关键词
D O I
暂无
中图分类号
V [航空、航天];
学科分类号
08 ; 0825 ;
摘要
The performance of 0.25, 0.3 and 0.35 mum fully-depleted SOI transistors is characterized between 77 and 300K. The behavior of device parameters such as drain current, mobility, transconductance, threshold voltage, subthreshold slope, and Early voltage is analyzed. The suitability of sub-micron FD-SOI devices is examined for low temperature operation as encountered in deep space exploration missions. The results indicate significant performance improvements with decreasing temperature down to 100K. A second effect dominates below this temperature, thus decreasing mobility and leading to other parameter degradations below 100K.
引用
收藏
页码:415 / 419
页数:5
相关论文
共 44 条
  • [21] Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 mu m
    Burns, JA
    Keast, CL
    Knecht, JM
    Kunz, RR
    Palmateer, SC
    Cann, S
    Soares, A
    Shaver, DC
    [J]. 1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 102 - 103
  • [22] Design Considerations of Sub-100nm Dual Material Gate Fully Depleted Silicon on Insulator (DMG-FD-SOI)
    Jafar, Norsyahida
    Soin, Norhayati
    [J]. ICSE: 2008 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2008, : 69 - 75
  • [23] Short-channel characteristics of variable-body-factor fully-depleted silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors
    Ohtou, T
    Nagumo, T
    Hiramoto, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (6A): : 3885 - 3888
  • [25] An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process
    Suda, Ikuo
    Kishida, Ryo
    Kobayashi, Kazutoshi
    [J]. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
  • [26] Correlation between low-frequency noise and interface traps of fully-depleted silicon-on-insulator tunneling FETs induced by hot carrier stress
    Shin, Hyun-Jin
    Song, Hyun-Dong
    Song, Hyeong-Sub
    Eadi, Sunil Babu
    Choi, Hyun-Woong
    Kim, Seong-Hyun
    Kim, Do-Woo
    Lee, Hi-Deok
    Kwon, Hyuk-Min
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2020, 59 (10)
  • [27] An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process
    Kobayashi, Kazutoshi
    Suda, Ikuo
    Kishida, Ryo
    [J]. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
  • [28] Analog and Short Channel Effects Performance of Sub-100 nm Graded Channel Fully Depleted Silicon On Insulator (SOI)
    Jafar, Norsyahida
    Soin, Norhayati
    [J]. MINO'09: PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS: ADVANCES IN MICROELECTRONICS, NANOELECTRONICS AND OPTOELECTRONICS, 2009, : 63 - 67
  • [29] DETERMINATION OF FLAT-BAND VOLTAGES FOR FULLY DEPLETED SILICON-ON-INSULATOR (SOI) METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETS)
    LYU, JS
    NAM, KS
    LEE, CC
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1992, 31 (9A): : 2678 - 2681
  • [30] Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect
    Kuo, JB
    Sun, EC
    Lin, MT
    [J]. EDMO2003: 11TH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRON DEVICES FOR MICROWAVE AND OPTOELECTRONIC APPLICATIONS, 2003, : 83 - 86