共 44 条
- [21] Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 mu m [J]. 1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 102 - 103
- [22] Design Considerations of Sub-100nm Dual Material Gate Fully Depleted Silicon on Insulator (DMG-FD-SOI) [J]. ICSE: 2008 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2008, : 69 - 75
- [23] Short-channel characteristics of variable-body-factor fully-depleted silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (6A): : 3885 - 3888
- [24] Short-channel characteristics of variable-body-factor fully-depleted silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors [J]. Ohtou, T, 1600, Japan Society of Applied Physics (44):
- [25] An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process [J]. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
- [27] An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process [J]. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
- [28] Analog and Short Channel Effects Performance of Sub-100 nm Graded Channel Fully Depleted Silicon On Insulator (SOI) [J]. MINO'09: PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS: ADVANCES IN MICROELECTRONICS, NANOELECTRONICS AND OPTOELECTRONICS, 2009, : 63 - 67
- [29] DETERMINATION OF FLAT-BAND VOLTAGES FOR FULLY DEPLETED SILICON-ON-INSULATOR (SOI) METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETS) [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1992, 31 (9A): : 2678 - 2681
- [30] Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect [J]. EDMO2003: 11TH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRON DEVICES FOR MICROWAVE AND OPTOELECTRONIC APPLICATIONS, 2003, : 83 - 86