The Gate-Bias Influence for ESD Characteristic of NMOS

被引：2

作者：

Liu, Juan ^{[1
]}

Fan, Hang ^{[1
]}

Li, Jianguo ^{[1
]}

Jiang, Lingli ^{[1
]}

Zhang, Bo ^{[1
]}

机构：

[1] Univ Elect Elect Sci & Technol China, State Key Lab Elect Thin & Integrated Device, Chengdu 610054, Peoples R China

来源：

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

ESD; gate-bias effect; NMOS; TCAD;

D O I：

10.1109/ASICON.2009.5351505

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46V to 7.8V with the negative gate bias changed from 0V to -10V, and reduced from 10.46V to 5.92V with the positive gate bias changed from 0V to 3V. Under appropriate gate bias, the ESD protection devices can obtain lower Vt1 and higher Vt2. It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.

引用

页码：1047 / 1050

页数：4

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