Test scheduling for network-on-chip with BIST and precedence constraints

被引：0

作者：

Liu, C ^{[1
]}

Cota, É ^{[1
]}

Sharif, H ^{[1
]}

Pradhan, DK ^{[1
]}

机构：

[1] Univ Nebraska, Omaha, NE 68182 USA

来源：

INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Network-on-a-Chip (NoC) is becoming a promising paradigm of core-based system. In this paper we propose a new method for test scheduling in No C The method is based on the use of a dedicated routing path for the test of each core. We show that test scheduling under this approach is NP-complete and present an ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an efficient heuristic. We then improve the heuristic by including BISTs and precedence constraints. Experimental results for the ITC'02 SoC benchmarks show that the new method leads to substantial reduction on test application time compared to previous work. The inclusion of BIST tests and precedence constraints provides a comprehensive solution for test scheduling in NoC.

引用

页码：1369 / 1378

页数：10

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