A current-mode, 3V, 20MHz, 9-bit equivalent CMOS sample-and-hold circuit

被引：0
|
作者：
Sugimoto, Y
Iida, T
机构：
来源：
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new current-mode, low-power, low-voltage and high-speed CMOS sample-and-hold circuit has been designed and fabricated. A new current-mode differential switching scheme has been adopted to eliminate errors caused by feedthrough injection from the sample switches. The experimental result yields 9-bit resolution in 9mW power dissipation, in a 20MHz clock frequency from a 3V power supply.
引用
下载
收藏
页码：685 / 686
页数：2
相关论文
共 40 条
  • [1] A current-mode CMOS sample-and-hold circuit for ADC
    Mahatthumthanant, Phinet
    Kamsri, Thawatchai
    Petchmaneelumka, Wandee
    Sungicabunchoo, Tiparat
    Riewruja, Vanchai
    2006 SICE-ICASE INTERNATIONAL JOINT CONFERENCE, VOLS 1-13, 2006, : 2819 - +
  • [2] A 20MHz Switched-Current Sample-and-Hold Circuit for Current Mode Analog Iterative Decoders
    Lo, Ming-Yam
    Ki, Wing-Hung
    Mow, Wai-Ho
    PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009), 2009, : 283 - 286
  • [3] Design of a sub-1.5 V, 20 MHz, 0.1% MOS current-mode sample-and-hold circuit
    Sugimoto, Y
    Sekiya, M
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (02) : 258 - 260
  • [4] Design of a sub-1.5 V, 20 MHz, 0.1% MOS current-mode sample-and-hold circuit
    Sugimoto Y.
    Sekiya M.
    Analog Integrated Circuits and Signal Processing, 1999, 20 (2) : 149 - 153
  • [5] Design of a 1V, 40MHz, current-mode sample-and-hold circuit with 10-bit linearity
    Sugimoto, Yasuhiro
    Imai, Shigeo
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 2
  • [6] The design of a 1V, 40MHz, current-mode sample-and-hold circuit with 10-bit linearity
    Sugimoto, Y
    Imai, S
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 132 - 135
  • [7] A 1.5V,100MS/s,12-bit Current-Mode CMOS Sample-and-Hold Circuit
    Hashemipour, O.
    Nabavi, S. G.
    PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOL 18, 2006, 18 : 128 - +
  • [8] A current-mode sample-and-hold circuit with high accuracy
    Ozkilic, Mustafa Cem
    Minaei, Shahram
    Turkoz, Sait
    2007 9TH INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND ITS APPLICATIONS, VOLS 1-3, 2007, : 180 - +
  • [9] A 1.5V 150MS/s current-mode sample-and-hold circuit
    Sedighi, B
    Rajaee, O
    Jahanian, A
    Bakhtiar, MS
    PROCEEDINGS OF THE 2005 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOL 2, 2005, : II91 - II94
  • [10] A 9 bit 400 MHz CMOS double-sampled sample-and-hold amplifier
    Roy, Sounak
    Banerjee, Swapna
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 323 - +
1234