A 9 bit 400 MHz CMOS double-sampled sample-and-hold amplifier

被引：2

作者：

Roy, Sounak ^{[1
]}

Banerjee, Swapna ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/VLSI.2008.78

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A fully differential CMOS sample and hold amplifier(SHA) is described here. The circuit is designed as a front end sampler of a low-power,high-speed analog to digital converter. The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption. Using 0.18 proportional to CMOS technology,a resolution of 9 bit has been achieved at a sampling rate of 400MHz. Also,to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized. Using a supply voltage of 1.8 V and a signal swing of 0.6V(pp) the circuit consumes approximately 10 mW of power.

引用

页码：323 / +

页数：2

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