A 9 bit 400 MHz CMOS double-sampled sample-and-hold amplifier

A fully differential CMOS sample and hold amplifier(SHA) is described here. The circuit is designed as a front end sampler of a low-power,high-speed analog to digital converter. The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption. Using 0.18 proportional to CMOS technology,a resolution of 9 bit has been achieved at a sampling rate of 400MHz. Also,to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized. Using a supply voltage of 1.8 V and a signal swing of 0.6V(pp) the circuit consumes approximately 10 mW of power.