A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-mu m CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than -68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V (pp) at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V (pp) full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.