A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal

被引：0
|
作者：
Tsung-Sum Lee
Chi-Chang Lu
机构：
[1] National Yunlin University of Science and Technology,Department of Electronic Engineering
[2] National Yunlin University of Science and Technology,Graduate School of Engineering Science and Technology
[3] Wu-Feng Institute of Technology,Department of Electrical Engineering
来源：
Analog Integrated Circuits and Signal Processing | 2005年 / 45卷
关键词：
CMOS analog integrated circuits; sample-and-hold circuits;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A new technique for realizing a high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The design consideration of the building blocks is described in detailed. A prototype circuit in a 0.5-μ m CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 200 MHz of sampling frequency with less than −56.5 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8Vpp. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.6 ns acquisition time at 0.8 V step input, and 0.8 Vpp full-scale differential input range are achieved. The circuit dissipates 4.8 mW with a ± 1.5 V power supply.
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页码：37 / 46
页数：9
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