A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal

被引：0

作者：

Lee, TS ^{[1
]}

Lu, CC ^{[1
]}

Yu, SH ^{[1
]}

Zhan, JT ^{[1
]}

机构：

[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Yunlin 640, Taiwan

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.

引用

页码：3111 / 3114

页数：4

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