A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier

被引：0
|
作者：
Hsu, CC [1 ]
Wu, JT [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2003年 / E86C卷 / 10期
关键词：
sample-and-hold circuits; switched-capacitor circuits; time-interleaved analog-to-digital converter;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm(2) and dissipates 33mW from a single 2.5V supply.
引用
收藏
页码：2122 / 2128
页数：7
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