A current-mode CMOS sample-and-hold circuit for ADC

被引：0

作者：

Mahatthumthanant, Phinet ^{[1
]}

Kamsri, Thawatchai ^{[1
]}

Petchmaneelumka, Wandee ^{[1
]}

Sungicabunchoo, Tiparat ^{[1
]}

Riewruja, Vanchai ^{[1
]}

机构：

[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Bangkok 10520, Thailand

来源：

2006 SICE-ICASE INTERNATIONAL JOINT CONFERENCE, VOLS 1-13 | 2006年

关键词：

sample-and-hold; subtracter; half-wave rectifier; current-mode;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a current-mode sample-and-hold circuit using 0.5 mu m CMOS technology. The input signal is sampled using a current subtracter and a half wave rectifier instead of a sampling switch used in the conventional sample-and-hold circuit. As a result, the switch feedthrough error is eliminated. The proposed circuit achieves high sampling frequency up to 100MHz and high accuracy. The performances of the proposed circuit are demonstrated by MICE simulation results.

引用

页码：2819 / +

页数：2

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