A current-mode, 3V, 20MHz, 9-bit equivalent CMOS sample-and-hold circuit

被引：0
|
作者：
Sugimoto, Y
Iida, T
机构：
来源：
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new current-mode, low-power, low-voltage and high-speed CMOS sample-and-hold circuit has been designed and fabricated. A new current-mode differential switching scheme has been adopted to eliminate errors caused by feedthrough injection from the sample switches. The experimental result yields 9-bit resolution in 9mW power dissipation, in a 20MHz clock frequency from a 3V power supply.
引用
下载
收藏
页码：685 / 686
页数：2
相关论文
共 40 条
  • [21] A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit
    Lee, Tsung-Sum
    Lu, Chi-Chang
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2011, 30 (05) : 883 - 898
  • [22] A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit
    Tsung-Sum Lee
    Chi-Chang Lu
    Analog Integrated Circuits and Signal Processing, 2009, 58 : 105 - 113
  • [23] A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit
    Tsung-Sum Lee
    Chi-Chang Lu
    Circuits, Systems, and Signal Processing, 2011, 30 : 883 - 898
  • [24] A 1V operational, 20Ms/s and 57dB of S/N, current-mode CMOS sample-and-hold IC
    Sugimoto, Y
    2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 207 - 208
  • [25] A 35MS/s and 2V/2.5V current-mode sample-and-hold circuit with an input current linearization technique
    Sugimoto, Yasuhiro
    Gohda, Yuji
    Tanaka, Shigeto
    2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 445 - 448
  • [26] LOW-VOLTAGE, HIGH-SPEED, AND HIGH-PRECISION CURRENT-MODE SAMPLE-AND-HOLD CIRCUIT
    SUGIMOTO, Y
    KAKITANI, H
    TSURUMI, H
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 1995, 78 (07): : 68 - 81
  • [27] A 3.3V-110MHz 10-bit CMOS current-mode DAC
    Park, SY
    Cho, HH
    Yoon, KS
    2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 2002, : 173 - 176
  • [28] Low-voltage, high-speed, and high-precision current-mode sample-and-hold circuit
    Sugimoto, Yasuhiro
    Kakitani, Hisao
    Tsurumi, Hiroyuki
    Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1995, 78 (07): : 68 - 81
  • [29] A 2V, 500 MHz and 3V, 920 MHz low-power current- mode 0.6 μm CMOS VCO circuit
    Sugimoto, Y
    Ueno, H
    IEICE TRANSACTIONS ON ELECTRONICS, 1999, E82C (07) : 1327 - 1329
  • [30] A 3 V 30 MHz analog CMOS current-mode bandwidth programmable integrator
    Yoon, KS
    Hyun, JS
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1997, E80A (10) : 1994 - 1999
1234