A 9-bit 80-MS/s CMOS pipelined folding A/D converter with an offset canceling technique

被引：6

作者：

Lee, Seung-Chul ^{[1
]}

Jeon, Young-Deuk ^{[1
]}

Kwon, Jong-Kee ^{[1
]}

机构：

[1] ETRI, IT Convergence & Components Lab, Taejon, South Korea

来源：

ETRI JOURNAL | 2007年 / 29卷 / 03期

关键词：

analog-to-digital converter (ADC); folding;

D O I：

10.4218/etrij.07.0206.0180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high, linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are +/- 0.6 LSB and +/- 1.6 LSB, respectively.

引用

页码：408 / 410

页数：3

共 50 条

[21] A 9-bit 215-MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System
Wu, Bo
Zhu, Shuang
Zhou, Yuan
Chiu, Yun
2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2014,
[22] A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter
Ali, AMA
Dillon, C
Sneed, R
Morgan, A
Kornblum, J
Wu, L
Bardsley, S
CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, : 391 - 394
[23] A 9-bit 50MS/s Asynchronous SAR ADC in 28nm CMOS
Cao, Tuan-Vu
Aunet, Snorre
Ytterdal, Trond
2012 NORCHIP, 2012,
[24] A 9-bit 50 MS/s CBSC Pipelined ADC Using Time-Shifted Correlated Double Sampling
Hsiao, Po-Chun
Chao, I-Jen
Hsu, Chung-Lun
Liu, Bin-Da
Huang, Chun-Yueh
Chang, Soon-Jyh
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
[25] An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique
Kim, Daehyeok
Park, Sunghyun
Lee, Munkyo
Nah, Sunphil
Song, Minkyu
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 86 (03) : 407 - 415
[26] An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique
Daehyeok Kim
Sunghyun Park
Munkyo Lee
Sunphil Nah
Minkyu Song
Analog Integrated Circuits and Signal Processing, 2016, 86 : 407 - 415
[27] A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS
Chung, Hayun
Ishikuro, Hiroki
Kuroda, Tadahiro
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (05) : 1232 - 1241
[28] A Low-Power 9-bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS
Akkaya, Ayca
Celik, Firat
Leblebici, Yusuf
2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
[29] 10-bit 100MS/s CMOS Pipelined A/D Converter with 0.59pJ/Conversion- Step
Kim, Moo-Young
Kim, Jinwoo
Lee, Tagjong
Kim, Chulwoo
2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 65 - 68
[30] A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors
Liu, Mengyu
Zhu, Sihui
Xu, Yue
MICROELECTRONICS JOURNAL, 2023, 131

← 1 2 3 4 5 →