A 9-bit 80-MS/s CMOS pipelined folding A/D converter with an offset canceling technique

被引：6

作者：

Lee, Seung-Chul ^{[1
]}

Jeon, Young-Deuk ^{[1
]}

Kwon, Jong-Kee ^{[1
]}

机构：

[1] ETRI, IT Convergence & Components Lab, Taejon, South Korea

来源：

ETRI JOURNAL | 2007年 / 29卷 / 03期

关键词：

analog-to-digital converter (ADC); folding;

D O I：

10.4218/etrij.07.0206.0180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high, linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are +/- 0.6 LSB and +/- 1.6 LSB, respectively.

引用

页码：408 / 410

页数：3

共 50 条

[11] An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR
Fan Ye
Long Cheng
Kaihui Lin
Junyan Ren
Analog Integrated Circuits and Signal Processing, 2010, 63 : 503 - 508
[12] A 9-Bit 123-MS/s Swiched-Current Pipelined ADC with OP Feedback and Offset Current Cancellation
Sung, Guo-Ming
Lin, Wen-Sheng
Li, Jiung-Shian
2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2013, : 673 - 676
[13] A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation
Feygin, G
Nagaraj, K
Chattopadhyay, R
Herrera, R
Papantonopoulos, I
Martin, D
Wu, P
Pavan, S
PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2001, : 153 - 156
[14] A SHA-less 10-bit 80-MS/s CMOS Pipe lined ADC
Jung, Young-Mok
Zhe, Jin
Kwon, Chan-Keun
Kim, Hoon-Ki
Kim, Soo-Won
2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1647 - 1649
[15] A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS
Wu, Bo
Zhu, Shuang
Zhou, Yuan
Chiu, Yun
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (03) : 839 - 849
[16] A 9-bit, 110-MS/s Pipelined-SAR ADC Using Time-Interleaved Technique with Shared Comparator
Kim, Taehoon
Kim, Sunkwon
Woo, Jong-Kwan
Lee, Hyongmin
Kim, Suhwan
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 170 - 174
[17] Design of a 11 bit 10Ms/s pipelined A/D converter
Peng, BL
Cheng, J
Chen, GC
2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 310 - 313
[18] A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique
Nam, Jae-Won
Jeon, Young-Deuk
Cho, Young-Kyun
Kwon, Jong-Kee
MICROELECTRONICS JOURNAL, 2011, 42 (11) : 1225 - 1230
[19] A 10-bit, 100 MS/s CMOS A/D converter
Kim, KY
Kusayanagi, N
Abidi, AA
PROCEEDINGS OF THE IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, : 419 - 422
[20] A 500 MS/s 10-bit CMOS D/A converter
Xiao, P
Shin, J
Soyuer, M
Stawiasz, K
1996 2ND INTERNATIONAL CONFERENCE ON ASIC, PROCEEDINGS, 1996, : 252 - 255

← 1 2 3 4 5 →