A 9-bit 80-MS/s CMOS pipelined folding A/D converter with an offset canceling technique

被引：6

作者：

Lee, Seung-Chul ^{[1
]}

Jeon, Young-Deuk ^{[1
]}

Kwon, Jong-Kee ^{[1
]}

机构：

[1] ETRI, IT Convergence & Components Lab, Taejon, South Korea

来源：

ETRI JOURNAL | 2007年 / 29卷 / 03期

关键词：

analog-to-digital converter (ADC); folding;

D O I：

10.4218/etrij.07.0206.0180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high, linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are +/- 0.6 LSB and +/- 1.6 LSB, respectively.

引用

页码：408 / 410

页数：3

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