Structural DfT Strategy for High-Speed ADCs

被引：0

作者：

Lechuga, Yolanda ^{[1
]}

Mozuelos, Roman ^{[1
]}

Martinez, Mar ^{[1
]}

Bracho, Salvador ^{[1
]}

机构：

[1] Univ Cantabria, Microelect Engn Grp, E-39005 Santander, Spain

来源：

EMERGING TRENDS IN TECHNOLOGICAL INNOVATION | 2010年 / 314卷

关键词：

Folding and interpolated A/D converters; Design-for-Test; Circuit simulation; Behavioral modeling; Simulink environment;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a Design-for-Test (DfT) approach for folded ADCs. A sensor DfT circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of defects can be detected. A fault evaluation is done considering a behavioral model to compare the coverage of the proposed test approach with a functional test. Afterwards, a fault simulation is used on a transistor level implementation of the ADC to establish the optimum threshold limits for the DfT circuit that maximize the fault coverage figure.

引用

页码：531 / 538

页数：8

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