High-speed ΣΔ modulators with reduced timing jitter sensitivity

As higher and higher frequency signals are sampled, clock jitter limits the achievable signal-to-noise ratio (SNR) in an analog-to-digital converter (ADC). This clock jitter limit is reviewed for upfront sampled ADCs and continuous-time (CT) sigma-delta modulators (SigmaDeltaMs). A pulse-shaped feedback digital-to-analog converter (DAC) is proposed to mitigate the jitter-imposed SNR limit in CT SigmaDeltaMs. An intuitive analysis that compares the pulse-shaped DAC to conventional DACs is presented. This analysis as well as a more rigorous analysis shows that the pulse-shaped feedback SigmaDeltaM has potential for significant SNR improvement over conventional CT SigmaDeltaMs as well as any upfront sampled system. For typical jitter, phase and amplitude noise numbers, SNR improvement is on the order of 17 dB over a conventional CT E AM and 8 dB over an upfront sampled ADC for a 1-GHz input.