A 1.0μm CMOS all-digital clock multiplier.

被引：0

作者：

Cheng, FKS ^{[1
]}

Chan, CF ^{[1
]}

Choy, OCS ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Elect Engn, Shatin, Hong Kong

来源：

40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A simple all-digital clock multiplies base on a digital-controlled oscillator technique. The locking sequence is separated into two stages, frequency and phase locking, to reduce time number of locking cycles. This all-digital clock multiplier can generate a clock with a frequency range from 21 MHz to 39 MHz.

引用

页码：460 / 462

页数：3

共 50 条

[1] An all-digital PLL clock multiplier
Olsson, T
Nilsson, P
2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 2002, : 275 - 278
[2] A High-Performance Low Complexity All-Digital Fractional Clock Multiplier
Abou-El-Kheir, Nahla T.
Mason, Ralph D.
Li, Mingze
Yagoub, M. C. E.
2019 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2019, : 73 - 76
[3] An All-Digital Despreading Clock Generator
Lee, I-Ting
Ku, Shih-Han
Liu, Shen-Iuan
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (01) : 16 - 20
[4] A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS
De Caro, Davide
Romani, Carlo Alberto
Petra, Nicola
Strollo, Antonio Giuseppe Maria
Parrella, Claudio
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (05) : 1048 - 1060
[5] All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology
Salem, Sanaz
Saneei, Mohsen
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2019, 103 : 1 - 12
[6] Design of an All-Digital, Low Power Time-to-Digital Converter in 0.18μm CMOS
Pokhara, Ankur
Agrawal, Jatin
Mishra, Biswajit
2017 7TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED), 2017,
[7] All-digital phase locked loop for clock recovery
Wei, H
Cheng, T
ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 3, 2005, : 395 - 398
[8] WIDE RANGE DIGITAL FREQUENCY MULTIPLIER.
Moffat, R.P.
Bhartia, P.
Clewes, T.W.
AEU-Archiv fur Elektronik und Ubertragungstechnik, 1977, 31 (06): : 258 - 260
[9] An All-Digital Clock Generator for Dynamic Frequency Scaling
Lin, Wei-Ming
Chen, Chao-Chyun
Liu, Shen-Iuan
2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 251 - +
[10] Novel universal all-digital clock smoothness technique
Qin, Xiao-Yi
Wang, Han-Sheng
Zeng, Lie-Guang
Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2001, 29 (09): : 1276 - 1279

← 1 2 3 4 5 →