A 1.0μm CMOS all-digital clock multiplier.

被引：0

作者：

Cheng, FKS ^{[1
]}

Chan, CF ^{[1
]}

Choy, OCS ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Elect Engn, Shatin, Hong Kong

来源：

40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A simple all-digital clock multiplies base on a digital-controlled oscillator technique. The locking sequence is separated into two stages, frequency and phase locking, to reduce time number of locking cycles. This all-digital clock multiplier can generate a clock with a frequency range from 21 MHz to 39 MHz.

引用

页码：460 / 462

页数：3

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