A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard

被引：0
|
作者：
Chotin, R [1 ]
Mehrez, H [1 ]
机构：
[1] Univ Paris 06, ASIM Lab, F-75252 Paris 05, France
来源：
ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present CESTAC, a method to control round-off errors in floating-point scientific computation, based on stochastic arithmetic. The real time use of this method suffers from bottleneck software calculation. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed hardware architecture has two parts a standard floating-point unit (FPU) and a unit dedicated to the control of round-off errors.
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页码：603 / 606
页数：4
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