A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard

被引：0
|
作者：
Chotin, R [1 ]
Mehrez, H [1 ]
机构：
[1] Univ Paris 06, ASIM Lab, F-75252 Paris 05, France
来源：
ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present CESTAC, a method to control round-off errors in floating-point scientific computation, based on stochastic arithmetic. The real time use of this method suffers from bottleneck software calculation. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed hardware architecture has two parts a standard floating-point unit (FPU) and a unit dedicated to the control of round-off errors.
引用
收藏
页码：603 / 606
页数：4
相关论文
共 50 条
  • [41] Development of an IP library of IEEE-754-standard single-precision floating-point dividers
    Ochi, H
    Suzuki, T
    Matsunaga, S
    Kawano, Y
    Tsuda, T
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (12): : 3020 - 3027
  • [42] Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers
    Ochi, Hiroyuki
    Suzuki, Tatsuya
    Matsunaga, Sayaka
    Kawano, Yoichi
    Tsuda, Takao
    [J]. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2003, E86-A (12) : 3020 - 3027
  • [43] How to half the latency of IEEE compliant floating-point multiplication
    Seidel, PM
    [J]. 24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2, 1998, : 329 - 332
  • [44] Floating-point arithmetic
    Boldo, Sylvie
    Jeannerod, Claude-Pierre
    Melquiond, Guillaume
    Muller, Jean-Michel
    [J]. ACTA NUMERICA, 2023, 32 : 203 - 290
  • [45] IEEE 754-2008 Decimal Floating-Point for Intel® Architecture Processors
    Cornea, Marius
    [J]. ARITH: 2009 19TH IEEE INTERNATIONAL SYMPOSIUM ON COMPUTER ARITHMETIC, 2009, : 225 - 228
  • [46] IMPLEMENTATION GUIDE TO A PROPOSED STANDARD FOR FLOATING-POINT ARITHMETIC
    COONEN, JT
    [J]. COMPUTER, 1980, 13 (01) : 68 - 79
  • [47] A CMOS FLOATING-POINT VECTOR-ARITHMETIC UNIT
    TIMMERMANN, D
    RIX, B
    HAHN, H
    HOSTICKA, BJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (05) : 634 - 639
  • [48] Design of Floating-Point Arithmetic Unit for FPGA with Simulink®
    Kralev, Jordan
    [J]. PROCEEDINGS OF 18TH INTERNATIONAL CONFERENCE ON SMART TECHNOLOGIES (IEEE EUROCON 2019), 2019,
  • [49] TUTORIAL ON PROPOSED IEEE STANDARD P754 ON BINARY FLOATING-POINT ARITHMETIC - ANN-ARBOR, MICHIGAN, 20TH MAY 1981
    GOSLING, JB
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1981, 128 (05): : 226 - 226
  • [50] Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication
    Nguyen, Tuan D.
    Bui, Son
    Stine, James E.
    [J]. 2018 IEEE 29TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), 2018, : 236 - 243
12345