Coherent chip-scale modeling for copper CMP pattern dependence

被引:0
|
作者
Cai, H [1 ]
Park, T [1 ]
Boning, D [1 ]
Kim, HJ [1 ]
Kang, YS [1 ]
Kim, S [1 ]
Lee, JG [1 ]
机构
[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In. this research, we present an improved and coherent chip-scale model framework for copper bulk polishing, copper over-polishing, and barrier layer polishing. The integration of contact wear and density-step-height models is more seamlessly implemented and addresses inherent shortcomings of the previous model. In the new model, a local density is used instead of the effective density computed by way of a planarization length, and only a contact wear coefficient is used to characterize the long-range planarization capability, thus avoiding the conflict between the planarization length and the contact wear coefficient in capturing topography variation. In addition, the pressure computed for each 240x240 mum block using contact wear is further redistributed, using a linear height vs. pressure model, among 40x40 mum cells within that block. The same model framework is used for different polishing steps, so that it is possible to directly compare basic process characteristics, such as pad stiffness, of different polishing stages. Results with the new model show a significant improvement of the modeling accuracy to less than 100 Angstrom of root mean square error. Furthermore, the new model framework can be adapted for the modeling of multi-level metallization processes.
引用
收藏
页码:63 / 70
页数:8
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