Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes

We present a characterization and modeling methodology for chip-level simulation of pattern dependencies in the fabrication of copper interconnect. The methodology integrates semi-empirical models for copper CMP and copper plating processes, and uses a specialized test mask and design of experiment for calibration purposes. We demonstrate the methodology with a four step copper CMP process and a superfill electroplating technology example.