Coherent chip-scale modeling for copper CMP pattern dependence

被引:0
|
作者
Cai, H [1 ]
Park, T [1 ]
Boning, D [1 ]
Kim, HJ [1 ]
Kang, YS [1 ]
Kim, S [1 ]
Lee, JG [1 ]
机构
[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In. this research, we present an improved and coherent chip-scale model framework for copper bulk polishing, copper over-polishing, and barrier layer polishing. The integration of contact wear and density-step-height models is more seamlessly implemented and addresses inherent shortcomings of the previous model. In the new model, a local density is used instead of the effective density computed by way of a planarization length, and only a contact wear coefficient is used to characterize the long-range planarization capability, thus avoiding the conflict between the planarization length and the contact wear coefficient in capturing topography variation. In addition, the pressure computed for each 240x240 mum block using contact wear is further redistributed, using a linear height vs. pressure model, among 40x40 mum cells within that block. The same model framework is used for different polishing steps, so that it is possible to directly compare basic process characteristics, such as pad stiffness, of different polishing stages. Results with the new model show a significant improvement of the modeling accuracy to less than 100 Angstrom of root mean square error. Furthermore, the new model framework can be adapted for the modeling of multi-level metallization processes.
引用
收藏
页码:63 / 70
页数:8
相关论文
共 50 条
  • [41] Plasmonics: the next chip-scale technology
    Zia, Rashid
    Schuller, Jon A.
    Chandran, Anu
    Brongersma, Mark L.
    MATERIALS TODAY, 2006, 9 (7-8) : 20 - 27
  • [42] A bright future for chip-scale packaging
    Chin, S
    ELECTRONIC PRODUCTS MAGAZINE, 1998, 40 (12): : 23 - 24
  • [43] Chip-scale atomic devices at NIST
    Knappe, Svenja
    Schwindt, Peter
    Gerginov, Vladislav
    Shah, Vishal
    Brannon, Alan
    Lindseth, Brad
    Liew, Li-Anne
    Robinson, Hugh
    Moreland, John
    Popovic, Zoya
    Hollberg, Leo
    Kitching, John
    14TH INTERNATIONAL SCHOOL ON QUANTUM ELECTRONICS: LASER PHYSICS AND APPLICATIONS, 2007, 6604
  • [44] CHIP-SCALE PACKAGING COMES TO THE FOREFRONT
    CHIN, S
    ELECTRONIC PRODUCTS MAGAZINE, 1995, 38 (06): : 17 - 18
  • [45] New stacked chip-scale package
    不详
    SOLID STATE TECHNOLOGY, 2001, 44 (03) : 42 - 42
  • [46] Magnetoencephalography with a chip-scale atomic magnetometer
    Sander, T. H.
    Preusser, J.
    Mhaskar, R.
    Kitching, J.
    Trahms, L.
    Knappe, S.
    BIOMEDICAL OPTICS EXPRESS, 2012, 3 (05): : 981 - 990
  • [47] Chip-scale power booster for light
    Kim, Jungwon
    SCIENCE, 2022, 376 (6599) : 1269 - 1269
  • [48] Commoditizing the uncommoditized: Chip-scale LiDAR
    Shin, Dongjae
    Hwang, Inoh
    Lee, Eunkyung
    Shin, Changgyun
    Lee, Jisan
    Byun, Hyunil
    Shim, Dongshik
    Jang, Bongyong
    Lee, Changbum
    Son, Kyunghyun
    Otsuka, Tatsuhiro
    Choo, Hyuck
    Ha, Kyoungho
    OPTICAL INTERCONNECTS XXII, 2022, 12007
  • [49] High power chip-scale laser
    Antman, Yair
    Gil-molina, Andres
    Westreich, Ohad
    Ji, Xingchen
    Gaeta, Alexander l.
    Lipson, Michal
    OPTICS EXPRESS, 2024, 32 (26): : 47306 - 47312
  • [50] Finite Element Analysis of Copper Pillar Interconnect Stress of Flip-chip Chip-Scale Package
    Afripin, Amirul
    Carpenter, Burt
    Hauck, Torsten
    2021 22ND INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2021,