A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 mu W/MHz power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.