Low Power Delay Locked Loop with All Digital Controlled SAR Delay Cell

A delay-locked loop (DLL) with the successive approximation register (SAR) circuit is proposed to achieve fast locking effect. In order to lower the power consumption, a loop state controller (LSC) is proposed. When the loop is locked, the path which goes through the register is chosen to enter the sleeping mode, and disable part of the circuit in the power saving mode. When entering the sleeping mode, the register provides the fixed input code; the phase error comparator (PEC) keeps tracking process, voltage, temperature, and load (PVTL) variation. Once a variation is occurred, the PEC sends a signal to the loop state controller (LSC) and enables the circuit from the sleeping mode to tracking mode when the clock needs to be locked again. The proposed DLL only needs 6 cycles to lock again. The simulated locking range is from 150MHz to 900MHz in the TSMC 0.18 mu m process. The power consumptions are 15mW in locking mode and 9mW in sleeping modes.