Novel architecture for on-chip AC characterization of I/Os

In nanometer technologies, the testing of I/O timing parameters is becoming more difficult and critical due to process complexities, thereby requiring the use of increasingly expensive test equipment and test time. To analyze the impact of process spread and to minimize the cost involved in characterization of I/O pin AC parameters, we present a comprehensive test system STIOBISC for on-chip measurement of I/O pin AC parameters such as Propagation Delay, Voltage Rise/Fall times and Maximum Operating Frequency with corresponding Duty Cycle variation. The proposed design gives the test engineer freedom to do complete testing on-chip on a large number of samples, with few opcodes using an inexpensive tester in a much shorter duration.