Implementation of a parallel SAD based wavefront sensor architecture on FPGA

被引:1
|
作者
Kincses, Zoltan [1 ]
Nagy, Zoltan [2 ]
Orzo, Laszlo [2 ]
Szolgay, Peter [2 ]
Mezo, Gyoergy [3 ]
机构
[1] Univ Pannonia, Dept Elect Engn & Informat Syst, Veszprem, Hungary
[2] Hungarian Acad Sci, Inst Comp & Automat, Cellular Sensory & Wave Comp Lab, Budapest, Hungary
[3] Heliophys Observat, Debrecen, Hungary
关键词
FPGA; wavefront sensor; SAD; ADAPTIVE OPTICS;
D O I
10.1109/ECCTD.2009.5275110
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wavefront aberration caused by turbulent or rapidly changing media can considerably degrade the performance of an imaging system. Adaptive optics can dynamically compensate these wavefront distortions and so provide corrected imaging. We developed an affordable adaptive optic system which combines CMOS sensor and LCOS display technology with the FPGA devices parallel computing capabilities. High speed and accurate wavefront sensor is fundamental part of any adaptive optic system. In this paper, an efficient FPGA implementation of the Sum of Absolute Differences (SAD) algorithm is introduced which accomplish correlation based wavefront sensing. This architecture was implemented on a Spartan-3 FPGA and is capable to measure the incoming wavefront at the speed of sensor data acquisition speed.
引用
收藏
页码:823 / +
页数:2
相关论文
共 50 条
  • [31] FPGA-based parallel ASIP architecture for reactive systems
    Buchenrieder, K
    Kress, R
    Pyttel, A
    Sedlmeier, A
    Veith, C
    ELECTRONICS LETTERS, 1997, 33 (10) : 842 - 843
  • [32] A Proposed FPGA-based Parallel Architecture for Matrix Multiplication
    Qasim, Syed Manzoor
    Abbasi, Shuja Ahmad
    Almashary, Bandar
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1763 - 1766
  • [33] Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
    Barranco, Francisco
    Tomasi, Matteo
    Diaz, Javier
    Vanegas, Mauricio
    Ros, Eduardo
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (06) : 1058 - 1067
  • [34] FPGA-Based Parallel Hardware Architecture For SIFT Algorithm
    Peng, J. Q.
    Liu, Y. H.
    Lyu, C. Y.
    Li, Y. H.
    Zhou, W. G.
    Fan, K.
    2016 IEEE INTERNATIONAL CONFERENCE ON REAL-TIME COMPUTING AND ROBOTICS (IEEE RCAR), 2016, : 277 - 282
  • [35] The implementation of adaptive optics wavefront spot extraction on FPGA
    Zhang, Yanyan
    Chen, Suting
    Li, Mei
    JOURNAL OF OPTICAL TECHNOLOGY, 2013, 80 (01) : 49 - 53
  • [36] Parallel Sorting based OS-CFAR Implementation in FPGA
    Sunny, Shine Parekkadan
    Narayanan, Prakash M.
    OCEANS 2022, 2022,
  • [37] An FPGA based Parallel Implementation for Point Cloud Neural Network
    Zheng, Xitao
    Zhu, Mingcheng
    Xu, Yuan
    Li, Yutong
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [38] Design and Implementation of Fast FPGA Based Architecture for Reversible Watermarking
    Ghosh, Sudip
    Kundu, Buoy
    Datta, Debopam
    Maity, Santi P.
    Rahaman, Hafizur
    2013 INTERNATIONAL CONFERENCE ON ELECTRICAL INFORMATION AND COMMUNICATION TECHNOLOGY (EICT), 2013,
  • [39] FPGA-Based Architecture for Implementation of Discrete Sine Transform
    Jain, Anamika
    Pandey, Neeta
    Jain, Priyanka
    ADVANCES IN SYSTEM OPTIMIZATION AND CONTROL, 2019, 509 : 13 - 22
  • [40] Design and implementation of FPGA based communication architecture for control system
    Zhang A.-K.
    Wang W.-M.
    Hu X.-H.
    Huang W.-J.
    Zhejiang Daxue Xuebao(Gongxue Ban)/Journal of Zhejiang University (Engineering Science), 2010, 44 (04): : 659 - 664