Design and implementation of FPGA based communication architecture for control system

被引：0
|
作者：
Zhang A.-K. [1 ]
Wang W.-M. [1 ]
Hu X.-H. [1 ]
Huang W.-J. [1 ]
机构：
[1] National Laboratory of Industrial Control Technology, Institute of Cyber-System and Control, Zhejiang University
来源：
Zhejiang Daxue Xuebao(Gongxue Ban)/Journal of Zhejiang University (Engineering Science) | 2010年 / 44卷 / 04期
关键词：
Channelredundancy; Communication architecture; CPLD; Distributed control system; FPGA; Hot swap;
D O I：
10.3785/j.issn.1008-973X.2010.04.006
中图分类号：
学科分类号：
摘要：
A high efficiency communication architecture applied in distributed control system (control system inner extending bus) was proposed to realize highly-efficient transmission and real-time control, and the design of its bus interface and bus protocol was detailed. The communication architecture, which is mainly consisted of field-programmable gate array (FPGA), complex programmable logic device (CPLD) and ARM7 CPU, implements hot swap on the target with high-speed transmission characteristics. As to the bus interfaces, the dual-channel and parallel communication method increase the system's transmission efficiency, and the redundancy between the two channels helps enhance the reliability of the communication. As to the bus structure, the highly-efficient secondary buffer and electrical expansion make the system very flexible. This communication architecture was put into effect on a system prototype, and the results show that it has high real-time performance and highreliability.
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页码：659 / 664
页数：5
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