Verification of submodeling technique in thermomechanical reliability assessment of flip-chip package assembly

被引:23
|
作者
Lai, YS [1 ]
Wang, TH [1 ]
机构
[1] Adv Semicond Engn Inc, Stress Reliabil Lab, Kaohsiung 811, Taiwan
关键词
D O I
10.1016/j.microrel.2004.09.007
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we verified the submodeling technique applied in the thermomechanical reliability assessment of a flip-chip BGA under accelerated thermal cycling test conditions. Since the steady-state creep model was implemented for the solder bump to better represent its realistic mechanical behavior, submodeling procedures developed specifically for path-dependent thermomechanical problems were considered. A detailed global model for the flip-chip BGA was built up to verify submodeling solutions. This model also served as a benchmark to examine solution discrepancies caused by different simplifications of the global model. (C) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:575 / 582
页数:8
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