The VLSI implementation of multistage decimation filter

被引：0
|
作者：
Yang, G [1 ]
Lin, ZH [1 ]
机构：
[1] Shanghai Jiao Tong Univ, VLSI Res Inst, Shanghai 200030, Peoples R China
来源：
PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN & COMPUTER GRAPHICS | 1999年
关键词：
comb filter; half-band filter; cannonic signed digit encoding (CSD); nest multiplication;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This paper presents a ROM programmable implementation of multistage decimation filter which is used in Sigma Delta ADC. Comb filter is adopted as the first stage filter.. Adders and subtracter are used to implement it. The last four times decimation is achieved by two half-band filters and a droop-correct FIR. The ALU performs all the arithmetic needed to implement these filters. The control words are stored in ROM. By programming the ROM coefficient, it can act as different kinds of filters. CSD coding technique, nested multiplication and RAM sub partition technique is adopted.
引用
收藏
页码：598 / 602
页数：3
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