ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology

被引：0
|
作者：
Juliano, PA
Anderson, WR
机构：
[1] Shrewsbury, MA 01545
[2] Intel Massachussetts, Hudson, MA 01749
来源：
JOURNAL OF ELECTROSTATICS | 2004年 / 62卷 / 2-3期
关键词：
ESD; SOI; CMOS; design; microprocessor;
D O I：
10.1016/j.elstat.2004.04.008
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We illustrate the complexity of designing ESD protection for a 64-bit microprocessor employing 140 million transistors. This IC contains 901 I/O signals, most operating at > 1 Gbit/s/pin, and 10 power supplies split into 27 domains. An extensive set of CAD tools used to expedite ESD-related chip assembly and to analyze finished layout is described. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码：113 / 131
页数：19
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