Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

被引：3

作者：

Voldman, S

Hui, D

Warriner, L

Young, D

Howard, J

Assaderaghi, F

Shahidi, G

机构：

[1] IBM Corp, Microelect Div, Semicond Res & Dev Ctr, Essex Junction, VT 05452 USA

[2] IBM Corp, Poughkeepsie, NY 12602 USA

[3] IBM Corp, Austin, TX 78758 USA

[4] IBM Corp, Rochester, MN 55901 USA

[5] IBM Corp, Semicond Res & Dev Ctr, Hopewell Junction, NY 12533 USA

[6] IBM Corp, Thomas J Watson Res Ctr, Yorktown Heights, NY 10598 USA

来源：

JOURNAL OF ELECTROSTATICS | 2000年 / 49卷 / 3-4期

关键词：

SOI; on-chip protection; ESD; CMOS; submicron IC technology; human body model;

D O I：

10.1016/S0304-3886(00)00016-4

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. (C) 2000 Elsevier Science B.V. All rights reserved.

引用

页码：151 / 168

页数：18

共 26 条

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Voldman, S
Hui, D
Warriner, L
Young, D
Howard, J
Assaderaghi, F
Shahidi, G
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