共 50 条
- [21] Deep sub-100nm CMOS with ultra low gate sheet resistance by NiSi 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 76 - 77
- [23] A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory 2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2005, : 23 - 26
- [24] Design and realization of sub 100nm gate length HEMTs 2001 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS, 2001, : 626 - 629
- [30] The gate misalignment effects of the sub-threshold characteristics of sub-100nm DG-MOSFETs 2002 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 2002, : 91 - 94