Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process

被引:64
|
作者
Chatterjee, A [1 ]
Chapman, RA [1 ]
Dixit, G [1 ]
Kuehne, J [1 ]
Hattangady, S [1 ]
Yang, H [1 ]
Brown, GA [1 ]
Aggarwal, R [1 ]
Erdogan, U [1 ]
He, Q [1 ]
Hanratty, M [1 ]
Rogers, D [1 ]
Murtaza, S [1 ]
Fang, SJ [1 ]
Kraft, R [1 ]
Rotondaro, ALP [1 ]
Hu, JC [1 ]
Terry, M [1 ]
Lee, W [1 ]
Fernando, C [1 ]
Konecni, A [1 ]
Wells, G [1 ]
Frystak, D [1 ]
Bowen, C [1 ]
Rodder, M [1 ]
Chen, IC [1 ]
机构
[1] Texas Instruments Inc, Ctr Semicond Proc & Design, Dallas, TX 75265 USA
关键词
D O I
10.1109/IEDM.1997.650507
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450 degrees C. Compared to pure SiO2, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g(m)) of 1000 mS/mm is obtained for L-gale=70 nm and t(OX)=1.5 nm. Peak cutoff frequency (f(T)) of 120 GHz and a low minimum noise figure (NFmin) of 0.5 dB with associated gain of 19 dB are obtained for t(OX)=2 nm and L-gate=80 nm.
引用
收藏
页码:821 / 824
页数:4
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