Gate technology for 70 nm metal-oxide-semiconductor field-effect transistors with ultrathin (<2 nm) oxides

Results are described for a gate level technology module developed to produce metal-oxide-semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EEL) using a thermal field-emission EEL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm. (C) 1997 American Vacuum Society.