A Novel Design of Low-Power Double Edge-Triggered Flip-Flop

被引：0

作者：

Yu, Chien-Cheng ^{[1
]}

Chen, Kuan-Ting ^{[2
]}

Wun, Jhong-yu ^{[1
]}

机构：

[1] Hsiuping Univ Sci & Technol, Dept Elect Engn, Taichung 41280, Taiwan

[2] Natl Chung Hsing Univ, Dept Elect Engn, Taichung 40227, Taiwan

来源：

PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT TECHNOLOGIES AND ENGINEERING SYSTEMS (ICITES2013) | 2014年 / 293卷

关键词：

Double edge-triggered flip-flop (DETFF); Power consumption; Power-delay product (PDP); Single edge-triggered flip-flop SETFF); IMPLEMENTATION;

D O I：

10.1007/978-3-319-04573-3_116

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Flip-flops are known and widely used in VLSI integrated circuit (IC) design. The main advantage of using double edge-triggered flip-flop (DETFF) is that it allows one to maintain a constant throughput while operating at only half the clock frequency. As the increasing usages for flip-flops, the desire to reduce power consumption has led to increased demand for low power consumption flip-flops. This paper compares four previously published DETFFs together with our design for their power consumption. Several HSPICE simulations with different input sequences show that the proposed DETFF reduces power consumption up to 79.5 %, as compared to the existing DETFFs.

引用

页码：947 / 955

页数：9

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