A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

被引：19
|
作者：
Varzaghani, A [1 ]
Yang, CKK [1 ]
机构：
[1] Univ Calif Los Angeles, Los Angeles, CA USA
来源：
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年
关键词：
analog-to-digital converter; signal-to-noise ratio; pipeline; resolution; effective number of bits; CMOS;
D O I：
10.1109/VLSIC.2004.1346585
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop pipeline structure has been investigated. We demonstrate a single-path 60OMS/s, 5bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total inputcapacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each pipeline-stage is digitally tuned. The chip is fabricated in 0.18mum. CMOS technology and consumes 70mW at 1.8V power-supply.
引用
收藏
页码：276 / 279
页数：4
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