Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

被引：0

作者：

Lee, DW ^{[1
]}

Kwong, W ^{[1
]}

Blaauw, D ^{[1
]}

Sylvester, D ^{[1
]}

机构：

[1] Univ Michigan, Ann Arbor, MI 48109 USA

来源：

4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I-gate, and subthreshold leakage, I-sub. The interaction between I-sub and I-gate complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I-sub and I-gate. We apply this method to ISCAS benchmark circuits in a projected 100nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.

引用

页码：287 / 292

页数：6

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