Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I-gate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both Igate and subthreshold leakage (I-sub). The interaction between I-gate and I-gate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I-gate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus HAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I-gate. We find that for technologies with appreciable I-gate, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I-sub reduction.