A High Speed Low Power 4:2 Compressor Cell Design

被引：0

作者：

Chang, Peng ^{[1
]}

Ahmadi, Majid ^{[1
]}

机构：

[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada

来源：

ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high speed low power 4:2 compressor cell design based on Domino Logic circuits. Two circuit level optimizations of 4:2 compressors are proposed by using Split Domino Logic and Multiple-output Domino Logic. All three designed circuits are simulated using HSPICE and compared with each other in terms of delay, power consumption, power-delay product, and operation frequency. Simulation results confirm the property of the design

引用

页码：157 / 160

页数：4

共 50 条

[31] Low-Power, High-Speed Adversarial Attack based 4:2 Compressor as Full Adder for Multipliers in FIR Digital Filters
Maddisetti, Lavanya
Ravindra, J. V. R.
2019 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), 2019,
[32] DESIGN OF AXIAL COMPRESSOR BLADING BASED ON TESTS OF A LOW SPEED COMPRESSOR.
McKenzie, A.B.
Proceedings - Institution of Mechanical Engineers, 1980, 194 : 103 - 111
[33] FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design
Ul Haq, Shams
Sharma, Vijay Kumar
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024, 33 (14)
[34] DESIGN AND ANALYSIS OF A LOW POWER CONSUMPTION HIGH SPEED FREQUENCY DIVIDER BY 2/3
Murtaza, Cristian
Cojan, Radu Adrian
2010 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1 AND 2, 2010, : 449 - 452
[35] Design, package and test of ultra high-speed low power 4:1 multiplexer
Zhou, He
Feng, Jun
Guan, Xin
Zhang, Li
Li, Wei
Guan, Zhiqiang
Dongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Southeast University (Natural Science Edition), 2009, 39 (02): : 234 - 237
[36] Design of a low power, high speed double tail comparator
Aakash, S.
Anisha, A.
Das, Jaswanth G.
Abhiram, T.
Anita, J. P.
PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT ,POWER AND COMPUTING TECHNOLOGIES (ICCPCT), 2017,
[37] Design of Low power and high speed 4-bit Comparator using Transmission Gate
Prajapat, Govind
Joshi, Akhilcsh
Jain, Aman
Verma, Kumkum
Jaiswat, Sanjay Kr.
2013 INTERNATIONAL CONFERENCE ON MACHINE INTELLIGENCE AND RESEARCH ADVANCEMENT (ICMIRA 2013), 2013, : 379 - 382
[38] Low power high speed design of a Reed Solomon decoder
Raghupathy, A
Liu, KJR
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 2060 - 2063
[39] Design of Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates
Alluri, Sudhakar
Dasharatha, M.
Naik, B. Rajendra
Reddy, N. S. S.
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 565 - 570
[40] Design of Low Power and High Speed Ripple Carry Adder
Archana, S.
Durga, G.
2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,

← 1 2 3 4 5 →