DESIGN AND ANALYSIS OF A LOW POWER CONSUMPTION HIGH SPEED FREQUENCY DIVIDER BY 2/3

被引：0

作者：

Murtaza, Cristian ^{[1
]}

Cojan, Radu Adrian ^{[1
]}

机构：

[1] Infineon Technol Romania SCS, Cluj Napoca, Romania

来源：

2010 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1 AND 2 | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design and performances of two high speed high frequency dividers in a standard 60 nm RF technology. The dividers are part of a wireless receiver using a synthesizer with a reference frequency of 26 MHz and a voltage controlled oscillator with an output frequency of 6 GHz. The input operating frequency range of the dividers is 2-8 GHz. The minimum input voltage range is 250mV peak-to-peak and the power consumption of each divider is less than 0.4mW for a 1.3-V power supply.

引用

页码：449 / 452

页数：4

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