Design of Low Power Consumption, High-Speed and Wide Division Ratio Range Programmable Frequency Divider

A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 um SiGe process is presented. The circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction counter and control logic. The combination of D flip-flops and logic gates effectively reduces the transmission delay and improves the operating frequency of the dual-modulus prescaler. The pulse counter and the swallow counter are merged into one, which reduces the chip area. A novel control logic is adopted to reduce the minimum frequency division ratio by allowing the S value equal to 0. The whole frequency divider is composed of TSPC (true-single-phase-clocked) D flip-flops and complementary CMOS logic gates without static power consumption. The simulation results indicate that the programmable frequency divider has a 4.7 GHz maximum operating frequency, and achieves a continuous division ratio range from 16 to 159, with a power consumption of 5.9 mA at 1.8 V supply voltage at the maximum operating frequency.