High Speed Wideband Low Phase Noise 2:1 Frequency Divider

The paper presents the design of a high-speed wideband low phase noise 2:1 frequency divider. A new differential D-latch topology for the divider is presented. Theoretical analysis and an optimization process for the design are given and various phenomena that dominate the speed, the bandwidth and the phase noise behavior of the frequency dividers are discussed. The simulation results show that the frequency divider has an input frequency range from 36 GHz to 6 CHz with a phase noise level of 137.7 dBc/Hz at an offset of 1 MHz, a core power of 12.58 mW and the core area of 70 mu mx105 mu m in a 90-nm CMOS process.