Floorplanning for 3D-IC with Through-Silicon Via Co-Design Using Simulated Annealing

被引：0

作者：

Zhu, Hai-Ying ^{[1
]}

Zhang, Mu-Shui ^{[1
]}

He, Yi-Fei ^{[1
]}

Huang, Yue-Hui ^{[1
]}

机构：

[1] Sun Yat Sen Univ, Sch Elect & Informat Technol, Guangzhou, Guangdong, Peoples R China

来源：

2018 JOINT IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 2018 IEEE ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC/APEMC) | 2018年

关键词：

3D-IC; floorplanning; TSV co-design; simulated annealing; SEQUENCE-PAIR; PLACEMENT; OPTIMIZATION; ALGORITHM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we will propose a method for floorplanning in three dimensional integrated circuits (3D-IC), considering the impact of Through-Silicon-Via (TSV). In 3D-IC, multiple device layers are vertically stacked and interconnected by excessive amount of TSVs which occupy a lot of silicon area and increase wire length. In this paper, a simulated annealing (SA) multi-objective optimization algorithm is developed for 3D-IC including the factors of floorplanning, plan functional block and TSV simultaneously. By using this SA method, we can get a floorplanning with minimum TSVs, thus reduces the silicon area and wire length.

引用

页码：550 / 553

页数：4

共 50 条

[41] Sensitivity Analysis of Through-Silicon Via (TSV) Interconnects for 3-D ICs
Zhao, Wen-Sheng
Hu, Jun
Yin, Wen-Yan
2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
[42] 3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections
Khan, Navas
Yu, Li Hong
Pin, Tan Siow
Ho, Soon Wee
Kripesh, Vaidyanathan
Pinjala, Damaruganath
Lau, John H.
Chuan, Toh Kok
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (02): : 221 - 228
[43] Coupling Analysis of Through-Silicon Via (TSV) Arrays in Silicon Interposers for 3D Systems
Xie, Biancun
Swaminathan, Madhavan
Han, Ki Jin
Xie, Jianyong
2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2011, : 16 - 21
[44] Study on copper protrusion of through-silicon via in a 3-D integrated circuit
Song, Ming
Wei, Zhiquan
Wang, Bingying
Chen, Liu
Chen, Li
Szpunar, Jerzy A.
MATERIALS SCIENCE AND ENGINEERING A-STRUCTURAL MATERIALS PROPERTIES MICROSTRUCTURE AND PROCESSING, 2019, 755 : 66 - 74
[45] Block-level 3D IC Design with Through-Silicon-Via Planning
Kim, Dae Hyun
Topaloglu, Rasit Onur
Lim, Sung Kyu
2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2012, : 335 - 340
[46] 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
Shen, Wen-Wei
Lin, Yu-Min
Chen, Shang-Chun
Chang, Hsiang-Hung
Chang, Tao-Chih
Lo, Wei-Chung
Lin, Chien-Chung
Chou, Yung-Fa
Kwai, Ding-Ming
Kao, Ming-Jer
Chen, Kuan-Neng
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 396 - 402
[47] Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design
Manna, Kanchan
Swami, Shivam
Chattopadhyay, Santanu
Sengupta, Indranil
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2016, 16 (01)
[48] Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration
Beyne, Eric
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (07): : 985 - 994
[49] Through-Silicon Via Design for a 3-D Solid-State Drive System with Boost Converter in a Package
Johguchi, Koh
Hatanaka, Teruyoshi
Ishida, Koichi
Yasufuku, Tadashi
Takamiya, Makoto
Sakurai, Takayasu
Takeuchi, Ken
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (02): : 268 - 276
[50] Multi-physical field coupling effect in micro pin-fin channel cooling with coaxial-like through-silicon via (TSV) for three-dimensional integrated chip (3D-IC)
Xu, Shiqi
Zhang, Yuanle
Li, Qiang
Chen, Xuemei
APPLIED THERMAL ENGINEERING, 2025, 258

← 1 2 3 4 5 →