Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration

This paper discusses the key technological aspects of via-middle Cu through-silicon vias (TSVs). The 3-D integration concept and the wafer front and backside process technology for realizing a 5-mu m-diameter, 50-mu m-deep Si TSV are described. Several options are shown for further, cost-effective, TSV scaling to 3-mu m diameter, while maintaining a 50-mu m Si thickness. Critical aspects for TSV reliability, such as barrier/liner integrity and Cu pumping, are discussed, and methods for a quantitative study are proposed. Finally, the impact of Cu via-middle TSVs on advanced electronic devices is discussed. A validated model for predicting the stress impact on devices and a method for defining possible keep-out zones are presented.