Floorplanning for 3D-IC with Through-Silicon Via Co-Design Using Simulated Annealing

被引：0

作者：

Zhu, Hai-Ying ^{[1
]}

Zhang, Mu-Shui ^{[1
]}

He, Yi-Fei ^{[1
]}

Huang, Yue-Hui ^{[1
]}

机构：

[1] Sun Yat Sen Univ, Sch Elect & Informat Technol, Guangzhou, Guangdong, Peoples R China

来源：

2018 JOINT IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 2018 IEEE ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC/APEMC) | 2018年

关键词：

3D-IC; floorplanning; TSV co-design; simulated annealing; SEQUENCE-PAIR; PLACEMENT; OPTIMIZATION; ALGORITHM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we will propose a method for floorplanning in three dimensional integrated circuits (3D-IC), considering the impact of Through-Silicon-Via (TSV). In 3D-IC, multiple device layers are vertically stacked and interconnected by excessive amount of TSVs which occupy a lot of silicon area and increase wire length. In this paper, a simulated annealing (SA) multi-objective optimization algorithm is developed for 3D-IC including the factors of floorplanning, plan functional block and TSV simultaneously. By using this SA method, we can get a floorplanning with minimum TSVs, thus reduces the silicon area and wire length.

引用

页码：550 / 553

页数：4

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